This disclosure relates generally to the field of semiconductor device fabrication, and more particular to fin field effect transistor (FinFET) fabrication.
Integrated circuits may comprise various semiconductor devices, including fin field effect transistors (finFETs). FinFETs are devices comprising three-dimensional layers of silicon, referred to as fins, that act as active channel regions, with gate regions located over the fins. FinFETs may be relatively small, high-performance devices. During formation of a finFET device, a plurality of fins may be formed on a substrate, and portions of these fins may be subsequently removed, or cut, to form isolation areas between the finFET devices. The gate regions are then formed over the remaining active fins after the isolation areas are formed. However, fin removal prior to gate formation may cause topography variations in the finFET device, which may lead to problems during subsequent processing steps, such as height differences between gates across the device, which may cause problems during contact formation. To reduce such topography variations, the fins in the isolation areas may alternatively be left in place and oxidized, while the active fins are protected by, for example, a nitride hardmask. However, oxidation of silicon causes an increase in volume in the oxidized fins versus the unoxidized, active fins. Additionally, the nitride hardmask that protects the active fins during oxidation may become more difficult to remove after being exposed to the oxidation, such that the etch that may be required to remove the oxidized nitride hardmask in order to complete processing of the active fins may also remove the oxidized fins. Therefore, fin oxidation may also cause topology variations in the finFET device, leading to similar issues during subsequent processing steps.